A conventional planar complementary metal oxide semiconductor (CMOS) transistor has four parts: a source, a drain, a channel disposed between the source and drain, and a gate disposed over the channel to control the channel. In planar CMOS transistors, the source, drain, and channel are formed by implanting ions into a planar semiconductor substrate, and the gate is then formed over a surface of the semiconductor substrate so as to overlie the channel. Engineers continuously seek to shrink the size of such transistors over successive generations of technology to “pack” more transistors into a given unit area, which provides consumers with devices that exhibit improved functionality.
One of the more recent advances in this continuing effort to shrink the size of CMOS transistors is the advent of fin field effect transistors (FinFETs). Unlike planar CMOS transistors where the source, drain, and channel are formed in a planar substrate; in FinFETs the source, drain, and channel region are formed in a thin slice of semiconductor material (i.e., a “fin”), which extends upward from the semiconductor substrate. A gate is then formed over the channel region in the fin. During operation, the gate is turned on to put the channel in a highly conductive state that allows electrons or holes to easily move from source to the drain. Conversely, when the gate is switched off, this conductive path in the channel region is supposed to disappear. Although this basic functionality is well established, unfortunately, it has been difficult to efficiently manufacture FinFETs that reliably withstand large voltages for high voltage and input/output circuit operations. Therefore, the present disclosure provides improved techniques for high-voltage FinFETs.